The invention relates to low-power digital filtering with the use of adaptive approximate filtering.
The increasing demand for battery-operated portable electronic devices has made the minimization of power consumption a critical design criteria in digital signal processing algorithm development. Applications for low-power signal processing include cellular telephones, pagers, laptop computers, portable Global Positioning System (GPS) receivers, portable camcorders, and other wireless communications devices. The power consumption of a digital system is proportional to the average number of computations that are required per output sample to accomplish the desired processing. Thus reducing the number of computations required to perform a particular task directly results in reduced power consumption.
Power reduction in signal processing systems generally involves optimization at all levels of the design abstraction including consideration of process technology, logic and circuit design, architecture design, and algorithm selection. Typically, optimization to lower the power consumption is done statically at design time. However, significant power gains can be achieved if the optimization is done dynamically at run time by considering and adapting to time-varying signal statistics.
A significant number of DSP functions involve frequency-selective digital filtering in which the goal is to reject one or more frequency bands while keeping the remaining portions of the input spectrum largely unaltered. Examples include lowpass filtering for signal upsampling and downsampling, bandpass filtering for subband coding, and lowpass filtering for frequency-division multiplexing and demultiplexing. The exploration of low-power solutions in these areas is therefore of significant interest.
To first order, the average power consumption, P, of a digital system may be expressed as: ##EQU1## where C.sub.i is the average capacitance switched per operation of type i (corresponding to addition, multiplication, storage, or bus accesses), N.sub.i is the number of operations of type i performed per sample, V.sub.dd is the operating supply voltage, and f.sub.s is the sample frequency.
Real-time digital filtering is an example of a class of applications in which there is no advantage in exceeding a bounded computation rate. For such applications, an architecture-driven voltage scaling process has previously been developed in which parallel and pipelined architectures can be used to compensate for increased delays at reduced voltages. This strategy can result in supply voltages in the 1 to 1.5 V range by using conventional CMOS technology. Power supply voltages can be further scaled using reduced threshold devices. Circuits operating at power supply voltages as low as 70 mV (at 300K) and 27 mV (at 77K) have been demonstrated.
Once the power supply voltage is scaled to the lowest possible level, the goal is to minimize the switched capacitance at all levels of the design abstraction. At the logic level, for example, modules can be shut down at a very low level based on signal values. Arithmetic structures (e.g. ripple carry vs. carry select) can also be optimized to reduce transition activity. Architectural techniques include optimizing the sequencing of operations to minimize transition activity, avoiding time-multiplexed architectures which destroy signal correlations, using balanced paths to minimize glitching transitions, etc. At the algorithmic level, the computational complexity or the data representation can be optimized for low power.
Another method to reduce the switched capacitance is to lower the parameter N.sub.i in equation (1). Efforts have been made to minimize N.sub.i by intelligent choice of algorithm, given a particular signal processing task. In the case of conventional filter design, the filter order is fixed based on worst case signal statistics, which is inefficient if the worst case seldom occurs. More flexibility may be incorporated by using adaptive filtering algorithms, which are characterized by their ability to dynamically adjust the processing to the data by employing feedback mechanisms.
In accordance with the invention, it will be illustrated how adaptive filtering concepts may be exploited to develop low-power implementations for digital filtering.